International Stress Workshop
The workshop will provide a forum for presenting current research and for discussions on issues related to stress-induced phenomena in microelectronics. The continued interconnect scaling and the development of 3D structures have brought new and significant challenges in process integration, design optimization and reliability. Stresses arising in interconnects and multi-chip stack structures due to thermal mismatch, microstructure changes and processing integration can lead to damage and failure of devices. Understanding stress-related phenomena in new materials and structures is critical for development of future metallization and 3D integration.
Stress-related phenomena generated by 3D integration and packaging extending beyond metal interconnects are of interest, focusing on device nanostructures and advanced 3D devices and memories. Multi-scale modeling and characterization developed for probing 3D structures are also of interest, as well as for 1D and 2D device structures, such as nanowires and flexible microelectronics.
Topics of interest include:
- Scaling effects of metal/low k structures, microstructure and reliability
- Ultra low k materials, electrical and mechanical properties of small dimensions
- Chip-package interaction and reliability impact in 3D integration
- Processing and reliability of TSV in 3D and die-stack structures
- Impact of interface and microstructure on reliability
- Synchrotron micro-diffraction on Cu stress and plasticity
- Solder joints and effect of intermetallics on reliability
- Multi-scale simulation and characterization
- Carbon-based materials and nanostructures: CNT and graphene structures
- 1D nanowires and 2D flexible structures for microelectronics
Following the spirit of previous workshops, new research results and advances in basic understanding are emphasized.